/************************************************************************************

 *    author : Jacl
 *    e-mail : 2320025806@qq.com
 *    date   : 20210109
 *    desc   : PRV564S config file
 *    version: 0.0

 __  __                   __           __         
/\ \/\ \                 /\ \__       /\ \        
\ \ \ \ \    ___     ____\ \ ,_\   ___\ \ \/'\    
 \ \ \ \ \  / __`\  /',__\\ \ \/  / __`\ \ , <    
  \ \ \_/ \/\ \L\ \/\__, `\\ \ \_/\ \L\ \ \ \\`\  
   \ `\___/\ \____/\/\____/ \ \__\ \____/\ \_\ \_\
    `\/__/  \/___/  \/___/   \/__/\/___/  \/_/\/_/

************************************************************************************/
/***********************************************************************************
                            注意事项
Cacheable Block设置方式：
    当地址和地址掩码（Cacheable_MASK）做与运算后，所得地址若等于Cacheable_ADDR则当前地址块
    可以被缓存。如当Cacheable_MASK=0xFFFF_FFFF_8000_0000,Cacheable_ADDR=0x0000_0000_8000_0000时
    地址0x0000_0000_8000_0000~0x0000_0000_8FFF_FFFF是可缓存区段
同理设定SFR 地址块
***********************************************************************************/



`define XLEN                    64                          //RV64 YES!
`define TLB_switch              1                           //TLB  YES!
`define ITLB_entry_NUM          16
`define DTLB_entry_NUM          16
`define DCacheForceInhibit      1                           //DCache force inhibit (InhibitDCache bit in kernel cfg is set to this value, can be change by software later)
`define ICacheForceInhibit      1                           //ICache force inhibit (as up)
`define CacheWTDefaultSwitch    1                           //DCache force write through mode default value
`define PADR                    32
`define Simulation              0                           //If 1, the files are Simulation-use
`define L1_switch               0                           //If 1, Cache is used; if 0 , ITCM is used
`define Mcop_switch             1                           //If 1, Math coprocessor is used, if 0, no math-coprocessor
`define PC_reset                64'h0000_0000_3000_0000
`define Cacheable_MASK          64'hFFFF_FFFF_8000_0000     // If Address & Cacheable_MASK = Cacheable_ADDR, then the space can be cache
`define Cacheable_ADDR          64'h0000_0000_8000_0000
`define SFR_ADDR_MASK           64'hFFFF_FFFF_FFFF_0000     // If Address & SFR_ADDR_MASK = SFR_ADDR_SEG, the address is in SFR segment
`define SFR_ADDR_SEG            64'h0000_0000_0200_0000
`define SFR_MTIME_ADDR          64'h0000_0000_0200_BFF8
`define SFR_MTIMECMP_ADDR       64'h0000_0000_0200_4000
`define SFR_MSOFTINT_ADDR       64'h0000_0000_0200_4008

`define AXI_DIFF 0
`define DEBUG_RUN 0
//`define WAVEDUMP
//`define STUCK_AUTO_STOP
